VLSI // TOOLSOPEN VLSI KOREA ↗ENGINEERING CONSOLE / FORMULA REGISTRY
Calculate.
Inspect.
Reuse.
Gross geometric estimate only; edge exclusion, scribe lanes, reticle limits and yield are omitted.
Twenty small tools.
Zero hidden assumptions.
입력, 단위, 공식, 경계, 버전과 결과가 같은 작업면에 남습니다. 결과는 검토용 추정치이며 sign-off를 대체하지 않습니다.
Frequency ↔ Period
Convert clock frequency in MHz to period in ns.
Digital / STAT(ns) = 1000 / f(MHz)02Setup Slack
Estimate setup slack from period and path delays.
Digital / STASlack = Period − Tcq − Comb − Setup + Skew03Dies per Wafer
Geometric gross-die estimate before edge exclusions and yield.
ManufacturingDPW ≈ π(D/2)²/A − πD/√(2A)04Poisson Yield
Simple Poisson yield model; not a production forecast.
ManufacturingY = exp(−D₀ × A)05DDR Bandwidth
Theoretical peak bandwidth from transfer rate and bus width.
MemoryGB/s = MT/s × bits / 8 / 100006Core Size
Estimate core area from standard-cell area and target utilization.
Physical DesignCore Area = Cell Area / Utilization07Chiplet Composite Yield
Independent-yield product for an illustrative multi-die assembly.
PackagingComposite Yield = ∏ die yields08RC Time Constant
Calculate first-order RC time constant.
Analog / Deviceτ = R × C09Hold Slack
Estimate a single-path hold margin with declared sign convention.
Digital / STASlack = Tcq_min + Comb_min − Hold − Skew10Clock Cycle Budget
Allocate a period after uncertainty and named path terms.
Digital / STABudget = Period − Uncertainty − Tcq − Setup11Pipeline Latency
Convert pipeline stages and clock period into ideal latency.
DigitalLatency = Stages × Period12SERDES Unit Interval
Convert a serial line rate to ideal unit interval.
InterfaceUI(ps) = 1,000 / Rate(Gb/s)13Packet Payload Efficiency
Compute payload share of named packet bytes.
InterfaceEfficiency(%) = Payload / (Payload + Overhead) × 10014Memory Capacity
Calculate raw capacity from depth and data width.
MemoryCapacity(bytes) = Depth × Width(bits) / 815SRAM Bitcell Array Area
First-order array-only area estimate.
MemoryArea(mm²) = Bits × BitcellArea(µm²) / 1,000,00016Dynamic Switching Power
Estimate idealized capacitive switching power.
PowerP(W) = α × C(F) × V² × f(Hz)17Junction Temperature Rise
First-order steady-state temperature rise through a declared thermal resistance.
PackagingΔT(°C) = Power(W) × θJA(°C/W)18Interconnect Resistance
Calculate resistance from length, resistivity and cross-sectional area.
Physical DesignR(Ω) = ρ(Ω·m) × L(m) / A(m²)19Via Array Current Share
Split a declared total current evenly across identical parallel vias.
Physical DesignI_via(mA) = I_total(mA) / N20Ideal ADC LSB
Calculate ideal quantization step from full-scale span and resolution.
Analog / DeviceLSB(V) = FullScaleSpan(V) / 2^NFrom timing to tapeout.
각 계산은 한 가지 질문만 빠르게 풀고, 복잡한 sign-off 조건은 명시적으로 경계 밖에 둡니다.
Planning a real tapeout?
MPW 프로그램을 찾고, die·yield·package 계산 결과를 같은 계획에 연결하세요.